This application claims the benefit of priority under 35 U.S.C. xc2xa7119 of Japanese Patent Application No. H11-184356, filed on Jun. 29, 1999, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates generally to a nonvolatile semiconductor memory device capable of electrically writing/erasing/reading out data and a method for producing the same. More specifically, the invention relates to a nonvolatile semiconductor memory device wherein memory cell transistors constitute a ground cell array, and a method for producing the same.
2. Description of the Related Background Art
FIGS. 14 and 15 show a conventional nonvolatile semiconductor memory device having a ground cell array structure. Of these figures, FIG. 14 is a perspective view three-dimensionally showing a nonvolatile semiconductor memory device, from which an interlayer dielectric film on word lines formed on a semiconductor substrate is removed. FIG. 15A is a plan view of the nonvolatile semiconductor device, and FIG. 15B is a sectional view taken along lines Axe2x80x94A of FIG. 15A.
As can be seen from FIG. 14, on the surface of a p-type semiconductor substrate 100 of this nonvolatile semiconductor memory device, element isolating regions 400 are formed by the LOCOS (Local Oxidation of Silicon) method. Between adjacent two of the element isolating regions 400, an element region 410 is formed. Below the element isolating regions 400, n+-type drain regions 140 and n+-type source regions 120 are formed. That is, the drain regions 140 and the source regions 120 are formed as impurity diffusion layers of the opposite conductive type to that of the semiconductor substrate 100.
The drain regions 140 and the source regions 120 are continuously connected to memory cells adjacent thereto in bit line direction. As can be seen from FIG. 15A, each of the drain regions 140 constitutes a bit line 141, and each of the source regions 120 constitutes a source line 121.
As can be seen from FIGS. 14 and 15B, a tunnel oxide film 200 having a thickness of about 100 angstroms is formed on the element regions 410, and floating gates 300 of a polycrystalline silicon are formed on the tunnel oxide film 200. On the floating gates 300, an insulating film 220 having a thickness of about 150 angstroms, which comprises three layers of an oxide film, a nitride film and an oxide film, is formed. On this insulating film 220, control gates 320 intersecting the bit lines 141 and the source lines 121 are formed. Each of the control gates 320 is made of a polycrystalline silicon similar to the floating gates 320. As can be seen from FIG. 15A, each of the control gates 320 constitutes a word line 131.
Then, the operation of this nonvolatile semiconductor memory device will be described. When data are written in a memory cell transistor of such a ground cell array, i.e., when electrons are injected into the floating gate 300, for example, a voltage of 6 V is applied to the bit line 141, a voltage of 10 V is applied to the word line 131, and the source line 121 is grounded. Thus, a channel current flows through the memory cell transistor, and a part thereof is injected into the floating gate 300 as hot electrons. After the electron injection, the threshold of the memory cell transistor is about 5 to 6 V.
When data are erased, for example, the bit line 141 is open, the word line 131 is grounded, and a voltage of 12 V is applied to the source line 121. Alternatively, the bit line 141 is open, a voltage of xe2x88x929 V is applied to the word line 131, and a voltage of 3 V is applied to the source line 121. Thus, the electrons of the floating gate 300 are emitted to the source line 121 (the source region 120). After the emission of the electrons, the threshold of the memory cell transistor is about 0 to 2 V.
When data are read, for example, a voltage of 3 V is applied to the bit line 141 and the word line 131, and the source line 121 is grounded. Thus, the presence of current flowing through the source line 121 is caused to correspond to 1-bit information xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. That is, when data are written, the threshold of the memory cell transistor is about 5 to 6 V, and when data are erased, the threshold of the memory cell transistor is about 0 to 2 V. Therefore, for example, when a voltage of 3 V is applied to the word line 131, a case where current flows from the bit line 141 to the source line 121 is caused to correspond to xe2x80x9c1xe2x80x9d, and a case where no current flows from the bit line 141 to the source line 121 is caused to correspond to xe2x80x9c0xe2x80x9d.
As can be seen from FIGS. 14, 15A and 15B, there is conventionally a limit to the high ration since the floating gate 300 is two-dimensionally formed on the surface of the semiconductor substrate 100.
It is therefore an object of the present invention to eliminate the aforementioned problems and to achieve the high density integration of a nonvolatile semiconductor memory device by three-dimensionally arranging source lines, bit lines and charge storage layers. That is, it is an object of the present invention to provide a nonvolatile semiconductor memory device capable of being integrated with high density by forming grooves in a semiconductor substrate, forming source lines or bit lines on the bottoms of the grooves and other portions than the grooves, respectively, and forming charge storage layers on the inner side wall portions of the groove.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a nonvolatile semiconductor memory device comprising: a plurality of memory cell transistors which are arranged in column and row directions; and a semiconductor substrate of a first conductive type, in which a plurality of grooves are formed so as to extend in column direction on the side of the surface thereof, each of the memory cell transistors comprising:
a first region of a second conductive type formed in the surface portion of the semiconductor substrate on the bottom of each of the grooves;
a second region of the second conductive type formed in the surface portion of the semiconductor substrate other than the grooves;
a charge storage layer formed on the inner side wall portion of each of the grooves; and
a conductive layer formed on the charge storage layer and the first and second regions via an insulating film.
According to another aspect of the present invention, a nonvolatile semiconductor memory device comprising: a plurality of memory cell transistors which are arranged in column and row directions; and a semiconductor substrate of a first conductive type, in which a plurality of grooves are formed so as to extend in column direction on the side of the surface thereof, each of the memory cell transistors comprising:
a first region of a second conductive type formed in the surface portion of the semiconductor substrate on the bottom of each of the grooves;
a second region of the second conductive type formed in the surface portion of the semiconductor substrate other than the grooves;
a charge storage layer formed on the semiconductor substrate; and
a conductive layer formed on the charge storage layer.
According to one aspect of the present invention, a method for producing a nonvolatile semiconductor memory device having a plurality of memory cell transistors which are arranged in column and row directions, the method comprising the steps of:
forming grooves in the surface portion of a semiconductor substrate of a first conductive type so as to extend in column direction;
forming a first insulating film on the semiconductor substrate including the inner side wall portion of the grooves;
forming charge storage layers on the first insulating film on the inner side wall portions of the grooves;
forming first regions of a second conductive type in the surface portion of the semiconductor substrate on the bottom of the grooves so as to extend along the grooves;
forming second regions of the second conductive type in a portion other than the grooves on the side of the surface of the semiconductor substrate so as to extend along the groove;
forming a second insulating film so as to cover the first and second regions and the charge storage layers; and
forming conductive layers on the second insulating film so as to extend in row direction.
According to another aspect of the present invention, a method for producing a nonvolatile semiconductor memory device having a plurality of memory cell transistors which are arranged in column and row directions, the method comprising the steps of:
forming grooves in the surface portion of a semiconductor substrate of a first conductive type so as to extend in column direction;
forming a first insulating film on the surface of the semiconductor substrate including the inner side wall portions of the grooves;
forming a second insulating film, which is an insulating film of a different kind from that of the first insulating film, on the first insulating film;
forming first regions of a second conductive type in the surface portion of the semiconductor substrate on the bottom of the grooves so as to extend along the grooves;
forming second regions of the second conductive type in the surface portion of the semiconductor substrate other than the grooves so as to extend along the grooves; and
forming conductive layers on the second insulating film so as to extend in row direction.